Date: Mon, 11 Nov 1996 17:25:10 GMT
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<title>CS 537 - Quiz #6</title>
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<b>UNIVERSITY OF WISCONSIN-MADISON
<br>
Computer Sciences Department</b>
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<b>CS 537
<br>
Spring 1996 </b>
<td><td align=right><b>Bart Miller</b>
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<td align=center><b>Quiz #6</b>
<br>
Wednesday, March 27
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<h2>Paging and Segmentation</h2>
Consider a virtual memory architecture with the following parameters:
<ul>
<li>
64 bit words
<li>
64 bit virtual addresses
<li>
8K byte page size
<li>
512K segments in a virtual address
<li>
4 gigabytes of real memory
<li>
page tables are stored in real memory
<li>
page tables can start on any byte boundary
</ul>
<p>
Show how a virtual address gets mapped into a real address.
Be sure to show
<ol>
<li>
how the various fields of each address are interpreted,
<li>
the size of each field (in bits),
<li>
the maximum number of entries each table could hold,
and
<li>
the maximum size possible for each table (in bytes).
</ol>
<p>
Draw and label a diagram to answer this question.
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<CENTER>
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<IMG ALIGN=CENTER SRC="q6.gif" ALT="Segments & Page Table">
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</CENTER>

<i>
<p>
The Segment Table has 512K entries times 64 bits (8 bytes), so has a
maximum size of 4 MB.
<p>
Each Page Table has 4G entries times 19 bits (rounded up to 24 bits or 3 bytes),
so has a maximum size of 12 GB.  Note that the extra bits in each PTE might
be used for R/W control or valid bits.
</i>

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<H4>
Last modified:
Fri Mar 29 13:14:23 CST 1996
by
<a href="http://www.cs.wisc.edu/~bart">bart</a></b>
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